1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same and, more particularly, to the semiconductor device and the method for manufacturing the same, in which the semiconductor device is provided with a seal ring for preventing water, moisture, and a like from penetrating into it through a dicing face of each of semiconductor dices separated from a semiconductor substrate by dicing.
The present application claims two priorities of Japanese Patent Application No.2003-026526 filed on Feb. 3, 2003 and Japanese Patent Application No.2003-113412 filed on Apr. 17, 2003, which are hereby incorporated by reference.
2. Description of the Related Art
A Large Scale Integration (LSI) such as a microprocessor or a memory known as a representative of semiconductor devices has become finer in size of each of its elements as higher levels of integration are achieved, so that correspondingly a size of a semiconductor region making up each of the elements has also become finer. Further, when forming a wiring line to be connected to each of the semiconductor regions, in order to reserve a high wiring density corresponding to a high integration density, it is not enough to form the wiring line only in a plane direction of a semiconductor substrate, so that multi-layer wiring technologies have been employed, by which the wiring lines are formed on a plurality of layers in a thickness direction of the semiconductor substrate. A multi-layer wiring structure including six to nine layers is realized in an example of a microprocessor, which is a representative of the LSIs.
In such the LSI that a multi-layer wiring structure is employed, a resistance value of the wiring lines has a large influence on characteristics such as an operating speed, so that the wiring line is desired to have a smaller resistance value. Conventionally, as a material of the wiring lines of semiconductor devices including LSIs, aluminum (Al) excellent in electrical characteristics, processability, and a like, or aluminum-based metal has been used generally. However, aluminum and aluminum-based metal (hereinafter may be referred simply to as aluminum-based metal) have a drawback of being low in electro-migration resistance, stress-migration resistance, and alike. Therefore, there is a recent tendency to replace aluminum-based metal with copper (Cu) or copper-based metal (hereinafter may be referred simply to as copper-based metal) that has a smaller resistance value and is excellent in electro-migration resistance, stress-migration resistance, or a like.
However, when forming the wiring lines using copper-based metal, a copper-based compound, which has a low vapor pressure, is difficult to pattern into a desired shape utilizing dry etching technologies as compared to aluminum-based metal. Therefore, to form the wiring line using copper-based metal, a known single damascene wiring technology is employed, by which after forming beforehand a wiring trench in a wiring insulating film formed on the semiconductor substrate and the copper-based metal film throughout a surface including this wiring trench, an unnecessary portion of the copper-based metal on the wiring insulating film is removed by Chemical Mechanical Polishing (CMP) so as to provide as the wiring line a portion of the copper-based metal film left (buried) only in the wiring trench. Further, a dual damascene wiring technology, which is an extension of the single damascene wiring technology, is employed, by which a structure suited for fine-patterned multi-layer wiring is realized.
In the dual-damascene wiring structure, on the semiconductor substrate on which a lower-layer wiring line is formed beforehand, an via insulating film (so-called an inter-layer dielectric) and a wiring insulating film are stacked, then a via hole and an upper-layer wiring trench are formed through these wiring insulating films respectively, then a copper-based metal film is formed throughout a surface, and then an unnecessary portion of the copper-based metal film is removed by CMP or a like so as to leave the copper-based metal film only in the via hole and the upper-layer wiring trench, thereby forming a via plug and an upper-layer wiring simultaneously. By such a configuration, the dual damascene wiring structure can be realized, in which the lower-layer and the upper-layer wiring are interconnected through the via plug.
Further, in the semiconductor device having the multi-layer wiring structure, a high-speed operation is affected by a signal delay due to, for example, an increase in inter-wiring line capacitance (hereinafter referred to also as capacitance simply) given by an wiring insulating film present between a lower-layer wiring line and an upper-layer wiring line or an increase in inter-wiring line capacitance caused by a decrease in plane directional inter-wiring-line interval caused by an improvement in fine patterning. Therefore, there is a tendency to use a low-dielectric constant film (“so-called” low-κ insulation film) as the wiring insulating film in order to reduce the capacitance due to the wiring insulating film.
In manufacture of the LSI, after necessary circuit elements are integrated on the semiconductor substrate in a condition where it is a wafer, the semiconductor substrate is separated into individual semiconductor dice by dicing. However, in this case, a dicing face of the semiconductor chip, that is, a sidewall of an wiring insulating film is exposed, so that water, moisture, and a like (hereinafter referred to as “water and a like”) penetrates through the dicing face, thus deteriorating moisture resistance. Especially, the LSI employing such a multi-layer wiring structure as described above has a larger number of wiring insulating film layers and so tends more to suffer from such deterioration in moisture resistance. It, therefore, may lead to a drawback such as an increase in leakage current or in dielectric constant of an originally low-dielectric constant film. To solve the drawback, it is desired to improve the moisture resistance.
Further, in manufacture of the LSI, when integrating necessary circuit elements on the semiconductor substrate in a condition where it is a wafer, various kinds of pads such as an assembly pad including a bonding pad for electrically interconnecting the circuit elements and an outside of the LSI, an intra-LSI characteristics evaluation pad, or a screening evaluation pad are provided on a surface of the semiconductor substrate. Then, for example, a wire is bonded to the assembly pad at the time of assembly of the LSI, while a test probe of an electrical measuring device is brought in contact with the characteristics evaluation pad or the screening evaluation pad at the time of, for example, product-shipment screening. To each of such pads formed on the surface of the semiconductor substrate beforehand, a load due to wire bonding or due to contact with the test probe is applied, so that a crack, a so-called pad crack, is likely to occur at such a portion of the semiconductor chip including an wiring insulating film directly below each of the pads. As a result, as described above, water and a like, if having penetrated through the dicing face, may get into the die through the pad crack, thus deteriorating moisture resistance. Therefore, it is necessary to take measures against pad cracks.
An LSI semiconductor device arranged to improve moisture resistance by preventing water and a like from penetrating through a dicing face as described above is disclosed in Japanese Patent Application Laid-open No. 2000-232104 (See pp. 3–5, FIG. 1.). As shown in FIG. 26, in the semiconductor device, between a circuit formation portion 102 and a dicing line portion 103 of a semiconductor chip 101, a seal ring 104 is provided in such a manner as to surround the circuit formation portion 102. In configuration, the seal ring 104 is formed by sequentially stacking: a tungsten plug 108 provided in each of three first seal trenches 106 formed in a first wiring insulating film 105 via the respective barrier metal layers 107; a first-layer metal electrode 109 that covers the tungsten plugs 108 entirely; a second tungsten plug 113 provided in each of two second seal trenches 111 formed in a second wiring insulating film 110 via respective barrier metal layers 112, to cover the first-layer metal electrode 109; and a second-layer metal electrode 114 that covers the second tungsten plugs 113 entirely.
In this configuration, even when semiconductor dice are separated from each other at the dicing line portion 103 by dicing to then expose a sidewall of each of wiring insulating films 105 and 110, water and a like penetrating into the semiconductor chip through its dicing face is blocked by the presence of the seal ring 104, thereby enabling improving moisture resistance.
The conventional semiconductor device as described in Japanese Patent Application No. 2000-232104 has a problem of insufficient moisture resistance at an interface between a wiring layer and an wiring insulating film that make up a seal ring 104, so that resultantly, even in such a configuration that a multi-tungsten plug structure is arranged as part of the seal ring 104, the LSI semiconductor device has a problem that its moisture resistance cannot sufficiently be improved.
That is, as shown in FIG. 26, the seal ring 104 provided to the LSI semiconductor device disclosed in the above patent document includes: the tungsten plugs 108 and 113 that are formed in such a manner as to surround the circuit formation portion 102 multiply; and the first-layer and second-layer metal electrodes 109 and 114 that are formed as one region physically. The first-layer and second-layer metal electrodes 109 and 114 are both stacked together with the second wiring insulating film 110.
An interface between each of the first-layer and second-layer metal electrodes 109 and 114 and the wiring insulating film 110 is generally low in moisture resistance, so that if chipping occurs at the time of dicing, water and a like penetrating through a dicing face readily reaches the first-layer and second-layer metal electrodes 109 and 114. As a result, the first-layer or second-layer metal electrode 109 or 114 starts deteriorating, so that the water and a like progressively penetrates further deeply beyond the first-layer or second-layer metal electrode 109 or 114. If the water and a like penetrates into the circuit formation portion 102, for example, a leakage current or a dielectric constant of the originally low-dielectric constant film increases, thus deteriorating reliabilities of the LSI semiconductor device. This tendency is especially remarkable at an upper part of the seal ring 104 because it has only the second-layer metal electrode 114 on it.
Further, the conventional semiconductor device described in the above patent document has a problem that the seal ring 104, which is shaped endlessly, encounters an induction current flowing through it if a magnetic field occurs during a process of manufacturing the LSI semiconductor device.
That is, although a film formation technology such as Chemical Vapor Deposition (CVD) or sputtering that utilizes plasma and a process technology such as dry etching are widely implemented in the LSI semiconductor device manufacturing process, such a process technology as to utilize plasma involves occurrence of a magnetic field, so that as shown in FIG. 27 a magnetic field H that has occurred in such a manner interlinks with the seal ring 104, on which a current I is induced. The result will be described as follows with reference to an example where plasma etching is performed to form, for example, copper-made wiring line. As shown in FIG. 28, such a phenomenon is observed that a copper layer 115 breaks out around a via hole 116 owing to an influence of the induced current. Therefore, the copper wiring line becomes defective, thus deteriorating a manufacture yield.
Further, the conventional semiconductor device described in the above patent document takes into account countermeasures against penetration of water and a like through the dicing face but not at all those against such pad cracks as described above.